V3I6P45

An Efficient Carry Select Adder with Less Delay and Reduced Area Application

Sivaiah Sankranti^1*,  B Ramyasree², C laxmi³

Abstract

Adders are fundamental building blocks in arithmetic and signal-processing systems. The overall performance of processors, digital signal processors (DSPs), and communication hardware is highly influenced by the efficiency of the adder architecture employed. Conventional Carry Select Adders (CSLAs) improve computational speed by pre-computing results for two possible carry inputs. However, this advantage is achieved at the cost of increased hardware resources and power consumption. This paper presents an efficient Carry Select Adder architecture that reduces delay, area, and power consumption through optimized carry generation and selection logic. The proposed design consists of a Half Sum Generator (HSG), Carry Generators (CG0 and CG1), Carry Selection Unit (CS), and Final Sum Generator (FSG). The architecture eliminates redundant logic operations and minimizes critical path delay. The design is implemented using Verilog HDL and synthesized using Xilinx Vivado. Experimental results demonstrate improved performance compared with conventional CSLA architectures in terms of delay, area utilization, and power consumption.

Keywords:

Carry Select Adder, VLSI, FPGA, Verilog HDL, Low Power Design, Area Optimization, Delay Reduction.